Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a semiconductor device with a buried gate and a method for fabricating the same.
In a sub 60-nanometer (nm) DRAM process, it may be advantageous to form a buried gate in order to increase the integration degree of transistors in a cell, simplify the process, and improve device characteristics such as a leakage characteristic.
A method for fabricating the buried gate is performed by forming a trench and burying a gate in the trench. Therefore, the interference between a bit line and the gate may be minimized, and the number of films to be stacked may be reduced. Furthermore, the capacitance of the cells may be reduced to thereby improve a refresh characteristic.
In general, after a buried gate is formed in a cell region, a sealing process may be performed for sealing the upper side of the buried gate using a gap-fill layer. A gate oxidation process and a gate conductive layer formation process may be performed to form a transistor of a peripheral circuit region by exposing only the peripheral circuit region. A contact etching process and a bit-line (BL) process may be performed to form a bit-line contact hole by exposing the cell region.
In this method, however, since a storage node contact hole is formed after the bit line is formed in the cell region, it is difficult to obtain an exposed contact area for forming the storage node contact hole. Furthermore, since the exposed contact area is narrow, interfacial resistance between a storage node contact and a substrate may increase.
In particular, when the process is performed on the basis of a design rule of 6F2, an active region in which a bit-line contact hole is to be formed should ideally be completely covered by the bit line. Therefore, when the area of the bit line is increased, an exposed contact margin for forming the storage node contact hole is further decreased.
To increase the process margin of the storage node contact hole, the storage node contact hole and the storage node contact may be formed before the bit line is formed. In order to prevent a bridge between the bit line and the storage node contact, the bit line should ideally be formed as large as possible. In this case, however, the area of the storage node contact is reduced to cause an increase in contact resistance.